ISL97635AIRZ【PDF 18/28 页】IC LED DRVR WHT/RGB BCKLGT 24QFN

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ISL97635A

Write Byte

The Write Byte protocol is only three bytes long. The first byte

starts with the slave address followed by the “command code,”

which translates to the “register index” being written. The third

byte contains the data byte that must be written into the register

selected by the “command code”. A shaded label is used on

cycles during which the slaved backlight controller “owns” or

“drives” the Data line. All other cycles are driven by the “host

master.”

used in other backlight controller specifications to avoid

confusion. Therefore, if the device is in the write mode where bit

0 is 0, the slave address byte is 0x58 or 01011000b. If the

device is in the read mode where bit 0 is 1, the slave address

byte is 0x59 or 01011001b.

The backlight controller may sense the state of the pins at POR

or during normal operation—the pins will not change state while

the device is in operation.

Read Byte

As shown in the Figure 21, the 4 byte long Read Byte protocol

MSB

LSB

starts out with the slave address followed by the “command

0

1

0

1

1

0

0

R/W

code” which translates to the “register index.” Then the bus

direction turns around with the re-broadcast of the slave

address with bit 0 indicating a read (“R”) cycle. The fourth byte

contains the data being returned by the backlight controller.

That byte value in the data byte reflects the value of the register

being queried at the “command code” index. Note the bus

DEVICE

IDENTIFIER

DEVICE

ADDRESS

directions, which are highlighted by the shaded label that is

used on cycles during which the slaved backlight controller

“owns” or “drives” the Data line. All other cycles are driven by

the “host master.”

Slave Device Address

The slave address contains in 7 MSB plus one LSB as R/W bit

but these 8 bits are usually called slave address byte. As

FIGURE 22. SLAVE ADDRESS BYTE DEFINITION

SMBus Register Definitions

The backlight controller registers are Byte wide and

accessible via the SMBus Read/Write Byte protocols. Their

bit assignments are provided in the following sections with

reserved bits containing a default value of “0”.

shown in Figure 22, the high nibble of the slave address byte is

0x5 or 0101b to denote the “backlight controller class.” Bit 3 in

the lower nibble of the slave address byte is 1. Bit 0 is always

the R/W bit, as specified by the SMBus protocol. Note: In this

document, the device address will always be expressed as a

full 8-bit address instead of the shorter 7-bit address typically

TABLE 2A. REGISTER LISTING

DEFAULT

SMBUS

ADDRESS

0x00

REGISTER

PWM

BIT 7

BRT7

BIT 6

BRT6

BIT 5

BRT5

BIT 4

BRT4

BIT 3

BRT3

BIT 2

BRT2

BIT 1

BRT1

BIT 0

BRT0

VALUE

0xFF

PROTOCOL

Read and Write

Brightness

Control Register

0x01

Device Control

Reserved

Reserved

Reserved

Reserved

Reserved

PWM_MD

PWM_SEL

BL_CTL

0x00

Read and Write

Register

0x02

Fault/Status

Reserved

Reserved

2_CH_SD 1_CH_SD

BL_STAT

OV_CURR

THRM_SHDN

FAULT

0x00

Read Only

Register

0x03

Identification

LED

MFG3

MFG2

MFG1

MFG0

REV2

REV1

REV0

0xC8

Read Only

Register

PANEL

0x07

DC Brightness

BRTDC7

BRTDC6

BRTDC5

BRTDC4

BRTDC3

BRTDC2

BRTDC1

BRTDC0

0xFF

Read and Write

Control Register

0x08

Configuration

Reserved

Reserved

Reserved

Reserved

Reserved

FSW

VSC1

VSC0

0xXF

Read and Write

Register

0x09

Output Channel

Reserved

Reserved

CH5

CH4

CH3

CH2

CH1

CH0

0xFF

Read and Write

Register

18

FN6564.2

December 22, 2008

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